Write-After-Read hazard (WAR)
Tag: war-hazard
Aliases: WAR, anti-dependence
A data hazard where a later instruction writes a register that an earlier instruction still needs to read. False dependence — eliminated by register renaming.
Lecture references
- L04 · Hazards — p.13 , p.15 , p.57
- L05 · Scoreboarding — p.6 , p.14 , p.15 , p.18 , p.32 , p.36 , p.37 , p.45 , p.49 , p.50 , p.51
- L06 · Tomasulo — p.8 , p.10 , p.11 , p.12 , p.14 , p.18 , p.22 , p.24 , p.30 , p.37 , p.38
- L07 · Interrupts & P6 — p.5 , p.8
- L08 · MIPS R10000 — p.14
- L09 · Memory Scheduling — p.5 , p.13
- L10 · Branch Prediction — p.6