Precise interrupts
Tag: precise-interrupts
Aliases: precise exceptions
An interrupt model in which the architectural state at the point of the interrupt is exactly the state after committing all earlier instructions and before any later instruction. Implemented via ROB-based in-order commit.
Lecture references
- L01 · Intro — p.4
- L03 · Pipelining — p.16
- L04 · Hazards — p.5
- L05 · Scoreboarding — p.5 , p.19 , p.21
- L06 · Tomasulo — p.44
- L07 · Interrupts & P6 — p.1 , p.3 , p.4 , p.10 , p.11 , p.12 , p.13 , p.14 , p.15 , p.17 , p.19 , p.20 , p.28 , p.32 , p.46 , p.48 , p.50 , p.51
- L08 · MIPS R10000 — p.9
- L09 · Memory Scheduling — p.9 , p.10 , p.49
- L10 · Branch Prediction — p.14